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| CYUSB301X EZ-USB FX3 USB 3.0外設(shè)解決方案 |
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| 文章來源： 更新時間：2014/9/18 9:55:00 |
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Cypress公司的CYUSB301X系列EZ-USB FX3是下一代USB 3.0外設(shè)控制器,具有可配置,并行和通用可編程接口GPIF II,能和任何處理器,ASIC或FPGA連接,和異步SRAM,異步和同步地址數(shù)據(jù)復(fù)用接口以及并行ATA無縫連接.器件還集成USB 3.和USB 2.0 PHY和32位ARM926EJ-S微處理器,從GPIF II到USB的數(shù)據(jù)傳輸速率達(dá)到375MBps,主要用在測試測量,數(shù)碼相機(jī),PDA,PMP,數(shù)字?jǐn)z像機(jī),視頻IP電話,工業(yè)照相機(jī),打印機(jī),掃描儀和醫(yī)療圖像設(shè)備等.本文介紹了CYUSB301X系列主要特性,邏輯框圖, 作為協(xié)處理器和主處理器的EZ-USB FX3,以及FX3™ SuperSpeed Explorer開發(fā)套件主要特性,框圖,電路圖,材料清單和PCB元件布局圖.
Cypress’s EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features.
FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and glueless connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA.
FX3 has integrated the USB 3.0 and USB 2.0 physical layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It implements an architecture that enables 375-MBps data transfer from GPIF II to the USB interface.
An integrated USB 2.0 OTG controller enables applications in which FX3 may serve dual roles; for example, EZ-USB FX3 may function as an OTG Host to MSC as well as HID-class devices.
FX3 contains 512 KB or 256 KB of on-chip SRAM for code and data. EZ-USB FX3 also provides interfaces to connect to serial peripherals such as UART, SPI, I2C, and I2S.
FX3 comes with application development tools. The software development kit comes with application examples for accelerating time to market.
FX3 complies with the USB 3.0 v1.0 specification and is also backward compatible with USB 2.0. It also complies with the Battery Charging Specification v1.1 and USB 2.0 OTG Specification v2.0.
CYUSB301X系列主要特性:
■ Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0
❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger adaptor (ACA) detection
■ General Programmable Interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices
❐ 8-, 16-, and 32-bit data bus
❐ As many as16 configurable control signals
■ Fully accessible 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512-KB or 256-KB embedded SRAM
■ Additional connectivity to the following peripherals
❐ I2C master controller at 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Ultra low-power in core power-down mode
❐ Less than 60 μA with VBATT on and 20 μA with VBATT off
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C operation at 1.2 V
■ Package option
❐ 121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)
❐ 131-ball, 4.7- × 5.1-mm, 0.4-mm pitch wafer-level chip scale package (WLCSP)
■ EZ-USB® software and development kit (DVK) for easy code development
CYUSB301X系列應(yīng)用:
■ Digital video camcorders
■ Digital still cameras
■ Printers
■ Scanners
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
■ Portable media players
■ Industrial cameras
圖1. CYUSB301X系列邏輯框圖
圖2. 作為協(xié)處理器的EZ-USB FX3
圖3. 作為主處理器的EZ-USB FX3
CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer開發(fā)套件
The FX3 SuperSpeed Explorer Kit is an easy-to-use and inexpensive development platform enabling developers to add USB 3.0 device functionality to any system.
The FX3 SuperSpeed Explorer Kit is an easy-to-use and inexpensive development platform enabling developers to add USB 3.0 device functionality to any system. The FX3 SuperSpeed Explorer Kit is built to evaluate and develop solutions with the CYUSB301x family of EZ-USB FX3 USB 3.0 peripheral controllers.
The EZ-USB® FX3 device is powered by a fully accessible ARM9 core with 512 KB of RAM. The FX3 device has a fully configurable, General Programmable Interface (GPIF™ II) that can interface with any processor, ASIC, image sensor, or FPGA.
The SuperSpeed Explorer Kit combines hardware, software, and documentation that enable customers to evaluate the FX3 device. This user guide describes the steps to install the software required by the SuperSpeed Explorer Kit and to operate the development board provided with the kit.
The guide also documents different types of firmware download and debug methods with detailed instructions. Two example projects(USBBulkSourceSinkLED and SRAM_FX3) explain the use of various features provided on the SuperSpeed Explorer Kit development board and the host applications provided with the FX3 SDK. This document also explains the hardware interfaces available on the development board.
FX3™ SuperSpeed Explorer開發(fā)套件包括:
■ FX3 development board
■ USB 3.0 A to B cable
■ Quick start guide
■ Jumpers
圖4. FX3™ SuperSpeed Explorer開發(fā)板外形圖
The development board provides convenient access to FX3 interfaces, such as GPIF II, I2C, SPI,UART, and I2S. The two 40-pin headers provide FX3 signals to connect to external boards using the GPIF II interface. Note that for convenience, the headers have long pins that extend above the top side of the PCB for use as test points or attachment to mating connectors. All GPIF II signals, which include a 32-bit data bus, 13 control lines, and a 100-MHz clock, are available to connect to external devices such as FPGAs, CPLDs, image sensors, or microcontrollers. The FX3 SDK examples help you program and evaluate these interfaces. The GPIF II interface supports 32-, 24-, 16-, and 8-bit data/modes; unused GPIF II pins can alternatively serve as GPIO pins if the GPIF II interface is not required.
圖5. FX3™ SuperSpeed Explorer開發(fā)板電路圖(1)
圖6. FX3™ SuperSpeed Explorer開發(fā)板電路圖(2)
圖7. FX3™ SuperSpeed Explorer開發(fā)板電路圖(3)
圖8. FX3™ SuperSpeed Explorer開發(fā)板電路圖(4)
圖9. FX3™ SuperSpeed Explorer開發(fā)板電路圖(5)
圖10. FX3™ SuperSpeed Explorer開發(fā)板電路圖(6)
圖11. FX3™ SuperSpeed Explorer開發(fā)板電路圖(7)
圖12. FX3™ SuperSpeed Explorer開發(fā)板電路圖(8)
圖13. FX3™ SuperSpeed Explorer開發(fā)板PCB元件布局圖:頂層
圖14. FX3™ SuperSpeed Explorer開發(fā)板PCB元件布局圖:底層 |
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